Memory systems including examples of calculating hamming distances for neural network and data center applications

ABSTRACT

Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory system including a Hamming processing unit. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at a processing unit having memory devices.

CROSS REFERENCE TO RELATED APPLICATION(S)

This application is a continuation of pending U.S. patent applicationSer. No. 17/016,023 filed Sep. 9, 2020. The aforementioned applicationis incorporated herein by reference, in its entirety, for any purpose.

BACKGROUND

Neural networks can provide output data which represent “labels” ofinput data. For example, in a type of neural network, input data isprovided to a set of layers in which some portion of the input data ismultiplied by a set of weights and accumulated in a transfer function(which may be nonlinear), to provide neural network output data. Thatoutput data may be referred to as labels, e.g., in a deep learningneural network environment. Labels may represent one or more aspects orfeatures of the input data.

A deep learning neural network environment may be interconnected amongvarious neural networks, e.g., the output of certain neural networks areprovided as input to other neural networks. Often, deep learning neuralnetworks may utilize large datasets, e.g., a facial image deep learningneural network can be trained on 8-million face images (like FaceNet).Large datasets, often being based on memory-intensive content likeimages or videos, demand increasing amounts of memory and increasingdata transfer requirements, like bandwidth or a number of memoryconnections to a processor, e.g., to retrieve the data of the datasetfor training or processing on the deep neural network.

Image content can be represented using a hash algorithm or a hash. Forexample, a hash can be applied to a particular image to represent thatimage as a binary embedding. That is a representation of the image is“embedded” into a binary representation or binary code. A particularbinary embedding can used as a way to match that image to another image,e.g., the respective binary embedding's of the two images are exactlythe same.

From information theory, a Hamming distance may be computed, among twonumerals (e.g., a binary number) of equal length, by identifying anumber of numeric positions in the numerals that are different (e.g.,different bits).

Moreover, there is an increasing interest in moving wirelesscommunications to “fifth generation” (5G) systems. 5G offers promise ofincreased speed and ubiquity, but methodologies for processing 5Gwireless communications have not yet been set. In some implementationsof 5G wireless communications, “Internet of Things” (IoT) devices mayoperate on a narrowband wireless communication standard, which may bereferred to as Narrow Band IoT (NB-IoT). For example, Release 13 of the3GPP specification describes a narrowband wireless communicationstandard.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic illustration of a system arranged in accordancewith examples described herein.

FIG. 2 is a schematic illustration of a method in accordance withexamples described herein.

FIG. 3 is a schematic illustration of a method in accordance withexamples described herein.

FIG. 4 is a schematic illustration of a system arranged in accordancewith examples described herein.

FIG. 5 is a schematic illustration of a method in accordance withexamples described herein.

FIG. 6 is a schematic illustration of a memory system arranged inaccordance with examples described herein.

FIG. 7 is a schematic illustration of a method in accordance withexamples described herein.

FIG. 8 illustrates an example of a system in accordance with aspects ofthe present disclosure.

DETAILED DESCRIPTION

Examples of systems and method described herein provide for theprocessing of image codes at various memory devices. Hamming image codesmay generated by various endpoint computing devices, such as Internet ofThings (IoT) computing devices, that receive or obtain images of theirsurrounding environments. As an example, a smartphone or camera devicemay obtain an image of a vehicle, like a car or a truck. Such devicescan generate a Hamming processing request, having an image code of theimage, to compare that representation of the image to other images. Inthe example, the image of the vehicle may be compared to other vehicleimages, e.g., to identify the vehicle. The Hamming processing requestmay be obtained at the computing device itself (e.g., in the example,the smartphone) or a network of computing devices (e.g., a data center)that can route the Hamming processing request to one or more memorydevices for processing of the image code. Accordingly, as part ofprocessing the image code, the memory device can compare the image codeto other image codes of respective images that are stored on the memorydevice. Advantageously, in processing the Hamming processing request atmemory devices themselves—in contrast to, for example, a processorrequesting and obtaining images at an associated memory (e.g., a cachememory) for comparison—the systems and methods described herein providefor efficient processing of Hamming image codes, with less memoryrequests being utilized in such systems because the comparison of theimages codes are occurring at the memory devices themselves. This may bereferred to as “edge” processing of image codes because the processing,including the comparison of image codes, are occurring at a processingunit having memory devices, at a memory controller coupled to memorydevices, or at the memory devices themselves.

Continuing the example of obtained image of an obtained vehicle image,an image code is generated based on various features of the obtainedvehicle image. In the example, features may include a color of thevehicle, words associated with a model/make of the vehicle (e.g., brandnames), aspects of the background of the image, a size of the vehicle inrelation to the background image, or other size aspects of the vehiclein relation to other aspects of the vehicle or background. Accordingly,an obtained vehicle image may be represented by various features. Thefeatures are used to calculate an image code for that vehicle image. Forexample, a hash, like a supervised semantics-preserving deep hashing(SSDH) algorithm, may be used to represent the features as a binaryembedding. The binary embedding can be referred to as an image code ofthe obtained image. While the example of an obtained image is withreference to an obtained vehicle image, it can be appreciated thatvarious types of images may be obtained. As another example, images ofindividuals or faces or individuals such that image codes can becalculated for any type of image, including those of individuals orfaces of individuals (e.g., for facial recognition purposes).Calculating image codes based on images of individuals or faces ofindividuals may be utilized in security applications, such asidentifying individuals in a dataset of convicted criminals.

With the image code, a Hamming processing request can be generated tocompare the image code of the obtained image to corresponding imagecodes of images stored on memory devices. For example, a hash can alsobe applied to the images stored on memory devices, to obtain image codesof the respective images for comparison with the image code of theobtained image. The comparison includes calculating respective Hammingdistances of the image code of the obtained image to each respectiveimage code of the respective images stored on the memory devices. Oncecalculated, a set of results may be obtained (e.g., using aK-nearest-neighbor algorithm) that is indicative of the “shortest”Hamming distances, e.g., for a binary embedding, the lowest values ofthe Hamming distances. This set of results indicates a set of storedimages that share the most features of the obtained image. Accordingly,using that set of results, various features of the obtained image may beidentified as corresponding to features obtained in the set of resultsor at least using the features of one result of the set of results.Additionally or alternatively, if the Hamming distance calculation isnull or zero, an “exact” match can be determined in that the obtainedimage has an image code that matches another image code of a storedimage. Accordingly, any information associated with that stored image(e.g., stored fields/parameters) may be inferred as features for theobtained image.

Advantageously, examples of systems and methods described herein may beused in neural networks (e.g., a deep learning neural network) tofacilitate the processing of datasets, which may include the use ofbinary embedding or image codes. Examples herein increase the rate andamount of processing of such datasets in neural network, as comparisonsof image codes (e.g., a binary embedding) can be performed “closer” tothe memory devices, e.g., at a processing unit having memory devices, ata memory controller coupled to memory devices, or at the memory devicesthemselves. By closer to the memory device herein is generally meantthat fewer interfaces and/or less latency may be provided by systemsdescribed herein relative to systems performing Hamming distancecalculations in a host computer. For example, when processing at thememory devices themselves, an IoT device may perform “edge” computing incomparing a given image to stored images on the IoT device itself, todetermine whether there is a set of results that matches that givenimage. Memory devices described herein, which may include non-volatilememories, can be utilized to facilitate processing of datasets in neuralnetworks; thereby increasing processing capacity of the calculationsperformed for the neural networks. Accordingly, the rate and amount ofprocessing of datasets in neural networks is increased, e.g., ascompared to a conventional neural network processing system, which mayfirst retrieve images or content from the memory devices to processimages or content at a local cache or storage device of an associatedhost computing device, introducing delays into processing speed andprocessing rates.

Additionally and advantageously, examples of system and methodsdescribed herein may increase the precision or accuracy of neuralnetworks, as a more efficient use of memory (e.g., via the increase ofthe rate and amount of processing) also may allow larger datasets to bestored on memory devices, thereby increasing the size of trainingdatasets and/or data to be processed/stored on the memory devices.Accordingly, a data center housing various pluralities of memory devicescan increase the speed of processing of datasets in neural networksusing the examples of systems and methods described herein. For example,a host computing device that includes a user application configured toexecute Hamming distance calculations may distribute processing of thosecalculations in generating Hamming processing requests to be processedby memory controllers coupled to the memory devices or processing unitshaving memory devices. In distributing the Hamming processing requests,the host computing device is not limited to a bus connection to thememory devices (e.g., a PCIe bus) that may have limited bandwidth or belimited to using local memory associated with the host computing deviceitself (e.g., a local cache memory or local storage device). Asdescribed herein, a Hamming processing unit (e.g. processor or memorycontroller) can process various Hamming distance calculations viaseveral buses (e.g., multiple PCIe buses) that are coupled to the memorydevices. For example, in various embodiments, one or more memorycontrollers and pluralities of memory devices can communicate via theNon-Volatile Memory Express (“NVMe”) protocol that facilitatesprocessing of memory access requests to the memory devices.

FIG. 1 is a schematic illustration of a system 100 arranged inaccordance with examples described herein. System 100 includes a hostcomputing device 102 coupled to IoT device 114 and IoT device 118.System 100 also includes Hamming processing unit 108 coupled to the hostcomputing device 102 via host bus 104. The Hamming processing unit 108includes host interface 110 that couples the host bus 104 between thehost computing device 102 and Hamming processing unit 108. The hostinterface 110 is coupled to a processor 116 including Hamming controllogic 112. The processor 116 is coupled to memory controllers 106 via arespective controller bus 120. Memory controllers 106 provide memoryaccess requests from the processor 116 to memory devices 124 (e.g., asgenerated by the Hamming control logic 112). The memory devices 124 arecoupled to respective memory controllers 106 via respective memory buses122.

The IoT device 114 can be a camera or include an image capture device,and the IoT device 118 can be implemented using a smartphone or includeimage capture device. The IoT devices 114 and 118 may capture images andprovide images to the host computing device 102. The host computingdevice 102 may obtain the images from the IoT devices 114 and 118, andfurther generate image codes based on the obtained images. For example,the host computing device 102 may host a neural network that utilizesimage codes, like binary embeddings, to process neural network requests(e.g., requests in a deep learning environment). The host computingdevice 102 may utilize a hash to generate respective image codes for theobtained images. A binary embedding may be generated using the hash torepresent an obtained image from IoT device 114 or IoT device 118. Eachbit of the binary embedding may represent an aspect, a feature, or adimension of the image, such that multiple dimensions may be categorizedas a binary value in the binary embedding. Accordingly, an image may berepresented as a binary embedding, and images that share one or morebits of the same corresponding value can be said to “match” that image.For example, a 128-byte binary embedding includes 1,024 bits (i.e., 8bits in a byte multiplied by 128). Each bit of the 1,024 may representan aspect of an image. Another image that shares a majority or most ofthe same bits as the 1,024 bits may match that binary embedding, therebyterming that compared image having that at least a portion of the sameimage code as a match. Accordingly, there is a need for systems andmethods to facilitate such matching in an efficient and fast manner.Advantageously, the systems and methods described herein, such as theHamming processing unit 108, distribute the calculations and comparisonsefficiently so that match images of a dataset can be identified fasterthan a conventional system which may rely on a local cache at hostcomputing device 102 to store and compare such images of a dataset.

One or more neural networks hosted on the host computing device 102(e.g., as part of a deep learning neural network environment) mayprocess large datasets to obtain neural network results about thedatasets. For example, a neural network on the host computing device 102may obtain an image from the IoT device 114, e.g., to identify a vehiclein the image as compared to other images in a large dataset of vehicleimages. To perform such a neural network identification, the neuralnetwork on the host computing device 102 generates a Hamming processingrequest to the Hamming processing unit 108, to obtain image processingresults about the obtained image using Hamming distance calculations.For example, the host computing device 102 may include a host processorconfigured to execute a user application utilizing Hamming distancecalculations to obtain image processing results about the obtainedimage. When executed, the user application generates a Hammingprocessing request to perform Hamming distance calculations on theobtained image with a dataset (e.g., a vehicle image dataset), to obtainthe image processing results about the obtained image. The imageprocessing results may be a set of results obtained from the Hammingprocessing unit 108. Continuing in the example, the set of results mayinclude or be indicative of certain vehicle images in a dataset ofvehicle images, with those vehicle images sharing at least one featureof the obtained image or a match of the vehicle in the obtained image,e.g., based on a comparison of image codes, as described herein.

The memory devices 124 are configured to store data including datasets,such as image or content datasets. For example, a dataset may be storedon the memory devices 124 if the Hamming processing unit 108 obtains,over the host bus 104, the dataset from one or more associated computingdevices. In the example, the one or more associated computing devicesmay be computing devices in a data center or a personal computing devicecoupled, via a network connection, to the Hamming processing unit 108.The Hamming processing unit 108 is configured to the store the dataset(e.g., images) among the memory devices 124. For example, the Hammingprocessing unit 108 may store discrete units of the dataset (e.g.,images or video frames) in the memory devices 124. In the examplesdescribed herein, the memory devices 124 may be non-volatile memorydevices, like a NAND memory device. The memory devices 124 may alsoinclude or more types of memory, including but not limited to: DRAM,SRAM, triple-level cell (TLC) NAND, single-level cell (SLC) NAND, SSD,or 3D XPoint memory devices. Data stored or data to be accessed on thememory devices 124 is communicated via the memory buses 122 from arespective memory controller 106. For example, the memory buses 122 maybe PCIe buses that operate in accordance with an NVMe protocol.

To obtain the set of results (e.g., a set of images of a dataset) fromthe memory devices 124 in the Hamming processing unit 108, the hostprocessor on the host computing device may also be configured togenerate the Hamming processing request and provide the Hammingprocessing request via the host bus 104 to the Hamming processing unit108 received at the host interface 110 of the Hamming processing unit108. For example, the host bus 104 may be a PCIe bus that cancommunicate processing requests between the host computing device 102and the Hamming processing unit 108. The host interface 110 isconfigured to receive Hamming processing requests from the hostcomputing device 102; for example, the host interface 110 may include aport configured to receive the Hamming processing request when detectedon the host bus 104. The host interface 110 is further configured toprovide the Hamming processing request to the processor 116 includesHamming control logic 112 configured to receive the Hamming processingrequest and to calculate a plurality of Hamming distances among adataset and the obtained image.

The Hamming processing request may include the image code associatedwith the obtained image, e.g., as hashed by the host computing device102. To perform the comparison of the image code of the obtained imageto images in a dataset (e.g., a vehicle image dataset), the Hammingcontrol logic 112 may include control instructions that, when executedby the processor 116, generate and provide memory access requests to thememory devices 124. Accordingly, the processor 116 including the Hammingcontrol logic 112, responsive to the Hamming processing request,generates one or more memory access requests (e.g., a read command) forthe memory devices 124 to access information associated with images inthe dataset. For example, the information accessed may be the imagesthemselves which are read from the memory devices 124, or theinformation accessed may be image codes representative of images in adataset. In the example, when the images themselves are accessed, theprocessor 116 may hash the images with the same hash that the hostcomputing device 102 applied to the obtained image from the IoT device114 or IoT device 118. While described in the examples herein as a readcommand, a memory access request may be various types of memory accessrequests. For example, in embodiments with multiple memory planes on amemory die, a memory access request may include a multi-plane readcommand, to read multiple planes on that memory die. As another example,in embodiments with multiple logical units (LUNs) of a memory device124, a memory access request can include a concurrent LUN read command.

In example implementations, the processor 116 may include any type ofmicroprocessor, central processing unit (CPU), an application specificintegrated circuits (ASIC), a digital signal processor (DSP) implementedas part of a field-programmable gate array (FPGA), a system-on-chip(SoC), or other hardware to provide Hamming distance calculations aspart of the Hamming processing unit 108.

Once the information is accessed from the memory devices 124, theHamming control logic 112 may be configured to control the processor 116to compare image codes of the dataset to the image code that wasprovided as part of the Hamming process request. To compare the imagecodes of the dataset to the image code that was provided as part of theHamming processing request, the Hamming control logic 112 is furtherconfigured to provide the processor 116 with control instructions tocalculate a respective Hamming distance for each image code of thedataset and the image code that was provided as part of the Hammingprocess request. In an implementation where the image codes are binaryembeddings or representations, a Hamming distance may be calculated foreach image code of the dataset and the image code of the obtained imageas provided in Equation (1).

d(p,q)=Σ_(i=1) ^(n)(q _(i) +p _(i))mod 2  (1)

where p is a bit of a binary image code as provided in the Hammingprocess request, q is a bit of a respective image code of an image inthe dataset, and n is the number of bits in the respective image codes.As indicated, a “mod 2” operation, being a modulo-2 calculation, isperformed after the summation of the bits. The results from eachmodulo-2 operation are summed to provide the Hamming distance for aparticular image code representing an image of the dataset and the imagecode that was provided as part of the Hamming processing request (e.g.,an image code of the obtained image from the IoT device 114 or IoTdevice 118).

In calculating a plurality of Hamming distances, the image code providedas part of the Hamming process request is compared to each image coderepresentative of a corresponding image of an image dataset. EachHamming distance calculation is representative of the obtained imagefrom the IoT device 114 or IoT device 118 being compared to an image ofdataset. To determine a match of the obtained image, a set of resultsmay be obtained by the processor 116 by executing a results algorithm toinclude matches in the set of results, as controlled by the Hammingcontrol logic 112. For example, the Hamming control logic 112 may beconfigured to apply a results algorithm, as executed by the processor116, as a threshold comparison, such that any Hamming distancecalculation passing a threshold is included in a set of results. Asanother example, a results algorithm may be executed by the processor116 as a null-test, such that only a null result for a Hamming distancecalculation is included in a set of results, which set may be unitary.As yet another example, a results algorithm may be executed by theprocessor 116 as a k-nearest neighbor algorithm (“k-nn” algorithm), suchthat a number of neighbors in a bitwise dimensional space are selectedas “nearest” to the image code of the obtained image based on thecalculated Hamming distance calculation of that respective image coderepresentative of an image of the dataset. In the example, the imagecode of the obtained image is defined as the “k” for k-nn algorithm; andeach image code representative of a corresponding image of an imagedataset is classified according to different labels (e.g., a label maybe image codes that have a Hamming distance of two bits to the imagecode of the obtained image). Continuing in the example, the set ofresults comprises the most frequent label(s) to the image code of theobtained image.

As additional or alternative example implementations of such resultsalgorithms, a results algorithm may be executed by the processor 116 asa null-test, such that only a null result for a Hamming distancecalculation is included in a set of results, which set may be unitary. Aresults algorithm may additionally or alternatively utilize a set ofcriteria for a match, such as a specified tolerance of matches, a matchwith minimum error (e.g., as compared to other matches), or any errorcriteria. For example, a threshold results algorithm may use an errorupper-bound to identify matches, such that matches are defined as thosewith errors that are under the error-upper bound. Accordingly, anynumber or results algorithms may be applied to the Hamming distancecalculations to identify a set of results indicative of certain imagesin the dataset that match the obtained image.

While examples of images codes being calculated in accordance with aHamming distance of hashed binary embedding have been described toidentity a matched image code of an obtained image, it can beappreciated that alternative hashing techniques may be utilized tocalculate image codes, such as perceptual hashing or feature hashing tocalculate image codes. Such hashing may utilize k-nn as a resultsalgorithm or alternative algorithms to compare results of calculatedimage codes. As an example of an alternative hashing technique, a Bloomfilter may be utilized to hash an obtained image and calculate imagecodes for a dataset. In the example, different than applying a modulo-2calculation as described with respect to Hamming calculations herein,images codes may be summed together, e.g., via an AND-operation toacquire sets of hashed image codes in varying distributions. Using thesummed sets of hashed image codes a control logic, like the Hammingcontrol logic 112 described herein, may identify which image codes sharea same set (e.g., a set of results) thereby indicating a match of theimage code representative of the obtained image.

Once identified as the set of results, the Hamming control logic 112 isconfigured to control the processor 116 to provide the set of results tohost computing device 102 via the host bus 104. For example, the set ofresults may be provided to the host computing device 102, in accordancewith control instructions of the Hamming control logic 112, as thecorresponding images of the dataset included in the set of results,which may be referred to as image processing results. Accordingly, thehost computing device 102 may utilize the provided set of results in aneural network hosted by the host computing device 102.

To perform the Hamming distance calculations, system 100 utilizes theHamming processing unit 108, including its Hamming control logic 112 andmemory controllers 106, to distribute processing of the memory accessrequests to the memory devices 124. The Hamming control logic 112 isconfigured to generate one or more memory access requests, which areprovided to the memory devices 124 via the memory controllers 106 andrespective memory buses 122. The Hamming control logic 112 provides thememory access requests to memory controllers 106 via respectivecontroller buses 120. Responsive to obtaining the memory access requestsfrom the Hamming control logic 112, the memory controllers 106 providerespective memory access requests, to multiple memory devices 124. Amemory controller 106 may utilize information in the memory accessrequest to identify which memory device 124 a memory access request isto be provided. For example, a memory controller 106 may utilize amemory address, provided in the memory access request (e.g. as headerinformation), and a corresponding table of memory addresses to identifya relevant memory device 124 for that memory access request. As anotherexample, a memory controller 106 may utilize a memory deviceidentification, whether logical or physical, provided in the memoryaccess request to identify a relevant memory device 124 for that memoryaccess request. Upon identifying a memory device 124 to provide thememory access request based on information in the memory access request,the memory controller issues the one or more memory access requests(e.g., a read command) to respective memory devices 124 to accessinformation associated with images in the dataset (e.g., image codes orimages themselves).

In utilizing the respective controller buses 120 and memory buses 122,the Hamming processing unit 108 may utilize multiple buses to accessinformation associated with images of a dataset, whether image codes orimages themselves, faster than a conventional system which may obtaininformation about the dataset over a single host bus 104 for processingat the host computing device 102. Accordingly, the system 100,advantageously, may increase the rate and amount of processing of suchdatasets in a neural network hosted on host computing device 102, ascomparisons of image codes are performed “closer” to the memory devices124, e.g., at the Hamming processing unit 108 having the memory devices124 via controller buses 120 and respective memory buses 122.

In various implementations, the memory controllers 106 may be NVMememory controllers 106, which are coupled to the processor 116 via arespective PCIe bus operating in accordance with an NVMe protocol. Thecontroller bus 120 may be an NVMe bus when operating in accordance withan NVMe protocol. In such implementations, the memory devices 124 may beNAND memory devices, which are coupled to the NVMe memory controllers106 via a respective PCIe bus operating in accordance with an NVMeprotocol. Accordingly, the memory buses 120 may be referred to as NVMememory buses. Accordingly, in comparison to a conventional memory systemwhich may access memory via a single host bus to host computing device102, the system 100, advantageously, may increase the rate and amount ofprocessing by the number of NVMe memory buses 120 connected torespective memory devices 124. Accordingly, in embodiments where theprocessor 116 is a FPGA, the system 100 may be referred to as“accelerating” Hamming distance calculations with an increaseavailability of data transfer over the memory buses 122.

FIG. 2 is a schematic illustration of a method 200 in accordance withexamples described herein. Example method 200 may be performed using,for example, a Hamming processing unit 108 that executes executableinstructions (e.g., execution by Hamming control logic 112 at theprocessor 116) to interact with the memory devices 124 via controllerbuses 120 and respective memory buses 122. For example, the operationsdescribed in blocks 202-206 may be stored as computer-executableinstructions in a computer-readable medium accessible by processor 116.In an implementation, the computer-readable medium accessible by theprocessor 116 may be one of the memory devices 124. For example, theexecutable instructions may be stored on one of the memory devices 124and retrieved by a memory controller 106 for the Hamming processing unit108 to execute the executable instructions for performing the method200. Additionally or alternatively, the executable instructions may bestored on a memory coupled to the host computing device 102 andretrieved by the processor 116 to execute the executable instructionsfor performing the method 300.

Example method 200 may begin with block 202 that start execution of themethod and includes an operation to obtain, over a host bus at aprocessor configured with Hamming control logic, a Hamming processingrequest to calculate a Hamming distance among a plurality of images andan image associated with an image code from a host computing device. Inthe example implementation of the Hamming processing unit 108, a Hammingprocessing request is obtained via host bus 104, e.g., from a hostcomputing device 102. For example, the host bus 104 may be a PCIe busthat couples the Hamming processing unit 108 to the host computingdevice 102, such that the host computing device 102 may provideinformation to the Hamming processing unit 108 from a user application,executing on a host processor, which utilizes Hamming distancecalculations and generates the Hamming processing requests. For example,the Hamming processing request, as generated by the user application,may specify that Hamming distance calculations regarding an image codeof an image and a dataset, including a plurality of images, stored onthe memory devices 124 are to be performed; and, accordingly, requests,by virtue of the Hamming process request, that the Hamming control logic112 implement such calculations at the Hamming processing unit 108. Inthe example, the Hamming process request may include the image codeassociated with the image. The image may be an image obtained from animage capture device, e.g., IoT device 114 or IoT device 118.Accordingly, in various implementations, at block 202, the Hammingcontrol logic 112 obtains the Hamming process request.

Block 202 may be followed by block 204, such that the method furtherincludes an operation, responsive to the Hamming processing request, toprovide at least one memory access request to a plurality of memorydevices to access information associated with the plurality of images.In the example implementation of the Hamming processing unit 108, theHamming control logic 112 executes an executable instruction to providememory access requests to the memory devices 124. For example,responsive to the Hamming processing request, the Hamming control logic112 generates one or more memory access requests (e.g., a read command)for the memory devices 124 to access information associated with imagesin a dataset having the plurality of images. For example, theinformation to be accessed may be the images themselves stored on thememory devices 124, or the information accessed may be image codesrepresentative of images in a dataset. In providing the memory accessrequests, the Hamming control logic 112 may include information in theat least one memory access requests for a memory controller (e.g.,memory controller 106) to identify which memory devices 124 the at leastone memory access requests are to be provided. For example, the Hammingcontrol logic 112 may include in (e.g., as header info) each at leastone memory access request a memory address of an image or image codeassociated with an image of the plurality of images, and/or a memorydevice identification for the image or the image code associated withthe image.

Block 204 may be followed by block 206, such that the method furtherincludes an operation to compare at least one image of the plurality ofimages to the image code to calculate a respective Hamming distance of aplurality of Hamming distances. In the example implementation of theHamming processing unit 108, the Hamming control logic 112 executes anexecutable instruction to compare at least one image of the plurality ofimages to the image code to calculate a respective Hamming distance. Forexample, the Hamming control logic 112 may execute executableinstructions at the processor 116 to calculate respective Hammingdistances for each image code of the dataset and the image code of theobtained image in accordance with Equation (1). Accordingly, eachHamming distance calculation is representative of the image code beingcompared to one of the plurality of images (e.g., respective images of adataset). The method 200 ends after execution of the block 206.

The blocks included in the described example method 200 are forillustration purposes. In some embodiments, these blocks may beperformed in a different order. In some other embodiments, variousblocks may be eliminated. In still other embodiments, various blocks maybe divided into additional blocks, supplemented with other blocks, orcombined together into fewer blocks. Other variations of these specificblocks are contemplated, including changes in the order of the blocks,changes in the content of the blocks being split or combined into otherblocks, etc.

FIG. 3 is a schematic illustration of a method 300 in accordance withexamples described herein. Example method 300 may be performed, forexample, by a host computing device 102 and/or a Hamming processing unit108 may execute executable instructions to interact with the memorydevices 124 via controller buses 120 and respective memory buses 122.For example, some instructions may be executed by a host processor athost computing device 102 (e.g., blocks 302-306), while otherinstructions may be executed by Hamming control logic 112 at theprocessor 116 (e.g., blocks 308-314). The operations described in blocks302-314 may be stored as computer-executable instructions in one or morecomputer-readable medium accessible by the host processor and/or byprocessor 116. For example, the executable instructions may be stored onone of the memory devices 124 and retrieved by a memory controller 106for the host computing device 102 and/or Hamming processing unit 108 toexecute the executable instructions for performing the method 300.Additionally or alternatively, the executable instructions may be storedon a memory coupled to the host computing device 102 and retrieved bythe processor 116 to execute the executable instructions for performingthe method 300.

Example method 300 may begin with block 302 that starts execution of themethod and includes an operation to obtain an image from an IoTcomputing device. In the example implementation, a host computing device102 obtains an image from IoT device 114 or IoT device 118. IoT devicesmay include image capture devices, such as a camera, and may captureimages to provide to the host computing device 102. In the exampleimplementation, the host computing device 102 may be configured toexecute, on a host processor of host computing device 102, a userapplication which is configured to obtain images from IoT device 114 orIoT device 118. Accordingly, the host computing device 102 may obtainimages as part of executing a user application that requests or utilizesimages.

Block 302 may be followed by block 304, such that the method furtherincludes an operation to generate an image code based on the using ahash. In the example implementation, the host computing device 102generates an image code for the obtained image using a hash. In theexample, the hash generates a binary embedding, which may referred to asimage code, to represent the obtained image from IoT device 114 or IoTdevice 118. As but one example, a SSDH algorithm may be used tocalculate an image code for the image. The host computing device 102 maybe configured to execute, on the host processor of host computing device102, a user application which is configured to hash images and generatecorresponding image codes.

Block 304 may be followed by block 306, such that the method furtherincludes an operation to generate a Hamming process request based on aneural network request to obtain image processing results using aplurality of Hamming distances. In the example implementation, a neuralnetwork (or one or more neural networks) on the host computing device102 requests image processing results regarding the obtained image and adataset (e.g., an image dataset). That neural network request may begenerated as part of a deep learning neural network environment, tomatch the obtained image to images in a dataset, or at least an image inthe dataset that shares one or more features/labels/aspects as theobtained image. The neural network request may include a request forimage processing results about the image and the dataset, therebygenerating a Hamming process request to calculate Hamming distances withrespect to where the images of the dataset are stored (e.g., the memorydevices 124). The Hamming process request includes the image code, suchthat the Hamming distances are calculated on the dataset with respect tothat image code. The Hamming processing request may be provided by thehost computing device 102 to a memory system, memory controller, ormemory device, which may be configured to execute that Hammingprocessing request, e.g., to interact with memory devices 124 where thedataset is stored. In the example implementation, the user applicationon the host computing device 102 is configured to generate the Hammingprocessing request and provide it to the Hamming processing unit 108 forcalculation of the plurality of Hamming distances with respect to theimage code.

Block 308 may be followed by block 306, such that the method furtherincludes an operation to obtain, over the host bus at a processor, aHamming processing request to calculate a Hamming distance. In theexample implementation, a Hamming control logic 112 at the processor116, obtains, over the host bus 104, the Hamming processing request tocalculate one or more Hamming distances with respect to the image codeprovided as part of the Hamming processing request. In the exampleimplementation, block 308 may be executed analogously as block 202 ofmethod 200. Accordingly, in various implementations, at block 308, theHamming control logic 112 obtains the Hamming process request.

Block 310 may be followed by block 308, such that the method furtherincludes an operation, responsive to the Hamming processing request, toprovide, at least one memory access request to a plurality of memorydevices to access information associated with the plurality of images.In the example implementation, a Hamming control logic 112 at theprocessor 116 executes the instruction to provide memory access requeststo the memory devices 124. In the example implementation, block 310 maybe executed analogously as block 204 of method 200. Accordingly, asdescribed above, responsive to the Hamming processing request, theHamming control logic 112 generates one or more memory access requests(e.g., a read command) for the memory devices 124 to access informationassociated with images in a dataset having the plurality of images.

Block 310 may be followed by block 312, such that the method furtherincludes an operation to obtain the plurality of images from theplurality of memory devices. In the example implementation, a Hammingcontrol logic 112 at the processor 116, obtains the plurality of imagesat a local cache or a local memory associated with the processor 116 forprocessing of the plurality of images, e.g., to calculate Hammingdistances, thereby comparing the image code with each image of theplurality of images. For example, the local memory or local cacheassociated with the processor 116 may be a static memory of the Hammingprocessing unit 108, such as a SRAM or a DRAM. In the exampleimplementation of obtaining the plurality of images, the memory devices124 may store only the images of dataset, and not corresponding imagecodes. Accordingly, the plurality of images are obtained at local cacheor memory, which is instructed by the Hamming control logic 112, to hashthe plurality of images with the same hash that was applied to theobtained image of the IoT device 114 or IoT device 118 to generate theimage code associated with that image. Thus, the Hamming control logic112 obtains the plurality of images from the memory devices 124 and mayalso hash the plurality of images to generate respective image codes foreach image of the plurality of images.

Block 310 may be followed by block 314, such that the method furtherincludes an operation to compare at least one image of the plurality ofimages to the image code to calculate respective Hamming distances of aplurality of Hamming distances. In the example implementation, block 314may be executed analogously as block 206 of method 200. For example, theHamming control logic 112 may execute instructions at the processor 116to calculate respective Hamming distances for each image code of thedataset and the image code of the obtained image in accordance withEquation (1). The method 300 may end after completion of the block 314.

The blocks included in the described example method 300 are forillustration purposes. In some embodiments, these blocks may beperformed in a different order. In some other embodiments, variousblocks may be eliminated. In still other embodiments, various blocks maybe divided into additional blocks, supplemented with other blocks, orcombined together into fewer blocks. Other variations of these specificblocks are contemplated, including changes in the order of the blocks,changes in the content of the blocks being split or combined into otherblocks, etc.

FIG. 4 is a schematic illustration of a system 400 arranged inaccordance with examples described herein. System 400 includes a hostcomputing device 102 coupled to IoT device 114 and IoT device 118.System 100 also includes memory controller 402 coupled to the hostcomputing device 102 via host bus 104. The memory controller 402includes host interface 408 that couples the host bus 104 between thehost computing device 102 and the host computing device 102. The hostinterface 408 is coupled to a processor 412 including Hamming controllogic 410. The host interface 408 and the processor 412 may also becoupled to the cache 404 via internal memory controller buses, forexample. The processor 412 is coupled to memory devices 124 via memoryinterface 406 and respective memory buses 416. The memory interface 406is also coupled to the cache 404, e.g., also via an internal memorycontroller bus. The cache 404 is coupled to an error correction unit 414that is configured to perform error correction on data communicated fromthe cache 404. Additionally or alternatively, it can be appreciated thatthe same numbered elements of system 100 and system 400 may beconfigured in an analogous way, such as host computing device 102, hostbus 104, IoT device 114, IoT device 118, and memory devices 124. Forexample, as previously described, the host bus 104 may be a PCIe busthat can communicate Hamming processing requests between the hostcomputing device 102 and, instead of the Hamming processing unit 108 ofFIG. 1 , the memory controller 402 of FIG. 4 . As another example, thememory devices 124 are configured to store data including datasets,e.g., datasets that the memory controller 402 obtains, over the host bus104, from one or more associated computing devices. And, as indicatedwith the same numbered element in FIG. 4 , the memory devices 124 mayinclude one or more types of memory, including but not limited to: DRAM,SRAM, TLC NAND, SLC NAND, SSD, or 3D XPoint memory devices.

Similar as described with respect to FIG. 1 , the host computing device102 may host a neural network that utilizes image codes, like binaryembeddings, to process neural network requests (e.g., requests in a deeplearning environment). Further, the host computing device 102 mayutilize a hash to generate respective image codes for the obtainedimages. Advantageously, in using the memory devices 124 and therespective memory buses 416, the memory controller 402 distributescalculations for the respective images codes and their comparisonsefficiently so that matched images of a dataset (e.g., a match to animage code of an obtained image) can be identified faster than aconventional system, which may rely on a local cache at host computingdevice 102 to store and compare such images of a dataset.

Continuing in an example of an obtained image from the IoT device 114,the neural network on the host computing device 102 generates a Hammingprocessing request to the memory controller 402, to obtain imageprocessing results about the obtained image using Hamming distancecalculations. The host computing device 102 may include a host processorconfigured to execute a user application utilizing Hamming distancecalculations to obtain image processing results about the obtainedimage. When executed, the user application generates a Hammingprocessing request to perform Hamming distance calculations on theobtained image with a dataset (e.g., a vehicle image dataset), to obtainthe image processing results about the obtained image. The hostcomputing device 102 provides the Hamming processing request to the hostinterface 408 via the host bus 104. When obtained by the host interface408, the host interface 408 is configured to provide the image codeassociated with the Hamming processing request to the cache 404 forstorage of that image code. As described herein, the memory controller402 utilizes the cache 404 with the stored, obtained image code tocalculate Hamming distances and compare them.

Recall that the Hamming processing request includes the image codeassociated with the obtained image, e.g., as hashed by the hostcomputing device 102. To perform the comparison of the image code of theobtained image to images in a dataset (e.g., a vehicle image dataset),images stored on memory devices 124 of that dataset also are to behashed for comparison to the stored image code at cache 404. In someexamples, image codes themselves of a dataset may be stored on thememory devices 124, in which case the calculations and comparisons canbe performed by the Hamming control logic 410 without hashing. In someimplementations, the cache 404 may be coupled directly to a storagedevice that is part of host computing device 102, like a SRAM or DRAMstorage device and obtain the image code to be stored directly from thestorage device. For example, the Hamming processing request provided tothe host interface 408 may include a memory access command that isprovided to the cache to access a storage device on the host computingdevice 102, to obtain the image code associated with the Hammingprocessing request. In various implementations, the cache 404 may be adynamic memory device, like a DRAM, and is configured to interact withthe processor 412. For example, the cache 404 may be a data cache thatincludes (e.g., as a multi-level cache) or corresponds to one or morecache levels of L1, L2, L3, L4, or any other cache level as will beunderstood by one of skill in the art.

To obtain images codes for calculation and comparison to the storedimage code at the cache 404, the Hamming control logic 410 may includecontrol instructions that, when executed by the processor 412, generateand provide memory access requests to the memory devices 124 via thememory interface 406 and memory buses 416. For example, the Hammingcontrol logic 410 may be configured to control the issuance of the oneor more memory access requests (e.g., a read command) to respectivememory devices 124 to access information associated with images in thedataset (e.g., image codes or images themselves) for the memorycontroller 402. In the example, the memory controller 402 identifies amemory device 124 to provide the information in the Hamming processingrequest, and the processor 412 uses that identification information togenerate one or more memory access requests. Accordingly, the Hammingcontrol logic 410, responsive to the Hamming processing request and asexecuted by the processor 412, generates one or more memory accessrequests (e.g., a read command) for the memory devices 124, coupled tothe memory controller 402, to access information associated with imagesin the dataset. For example, the information accessed may be the imagesthemselves which are read from the memory devices 124, or theinformation accessed may be image codes representative of images in adataset. The memory interface 406, interacting with the processor 412via an internal memory controller bus, is configured to provide the oneor more memory access requests to the memory devices 124 via respectivememory buses 416. Thus, the memory buses 416 coupling the memory devices124 to the memory controller 402 provide the stored information (e.g., adataset of image codes and/or images) for calculation and comparison ofHamming distances to an image code of an obtained image.

In example implementations, the processor 412 may include any type ofmicroprocessor, central processing unit (CPU), an application specificintegrated circuits (ASIC), a digital signal processor (DSP) implementedas part of a field-programmable gate array (FPGA), a system-on-chip(SoC), or other hardware to provide Hamming distance calculations aspart of the memory controller 402.

Responsive to the one or more memory access requests, the memory devices124 provide access to the requested information, e.g., informationassociated with images in the dataset, such as the image codes or theimages themselves. With access available at the memory devices 124, thememory interface 406 is further configured to provide the requestedinformation through the memory buses 416 and an internal memorycontroller bus between the memory interface 406 and the cache 404,whether image codes or images, to the cache 404 for storage.Accordingly, the cache 404 obtains the requested information, whetherimage codes or images, via the memory devices 124 and their respectivememory buses 416.

In the example implementation when the images themselves are accessed,the processor 412 may hash the images with the same hash which the hostcomputing device 102 applied to the obtained image from the IoT device114 or IoT device 118. Continuing in the example, the memory interface406 may provide the images themselves to the processor 412 for hashing;and, once hashed, the processor 412 may provide the image codes of theretrieved images back to the cache 404 via an internal memory controllerbus. In an example, the internal memory controller bus between theprocessor 412 and the cache 404 may be an AXI bus.

In some implementations, the cache 404 may be configured to provide theinformation obtained from the memory devices 124 (e.g., images or imagecodes) to the error correction unit 414 to error correct that obtainedinformation, and, subsequently, to receive the information from theerror correction unit 414 as error-corrected. The error correction unit414 is configured to error correct data or information obtained from thememory devices 124. For example, the error correction unit 414 may beconfigured to error correct data in accordance with a desired bit errorrate (BER) of operation for the memory devices 124. For example, theerror correction unit 414 may include a low-density parity-checkcorrection unit that is configured to error correct data in accordancewith a low-density parity-check code. In utilizing the error correctionunit 414, the memory controller 402 may correct errors that may occur todata during memory retrieval or storage at memory devices 124. Suchimplementations may be used depending on whether a desired BER isspecified by the host computing device 102 or a user executing a userapplication at the host computing device 102. In variousimplementations, as described herein, the error correction unit 414 maynot error correct data obtained from the memory devices 124, such asbecause the data obtained comprises binary embedding as the image codes.Because the host computing device 102 obtains image processing resultsas a set of neural network results that are indicative of the closestmatches a bit difference in some of the set of neural network resultsmay not result in any difference in results, e.g., as to the same set ofneural network results that would have been obtained using the errorcorrection unit 414. For example, depending on the length of the imagecodes used in the Hamming distance comparison, the respective Hammingdistance calculations in such systems may not vary significantly so asto obtain a different set of neural network results. Accordingly, theoptional implementations using the error correction unit 414 may beutilized when a desired BER of operation for the memory devices 124 isspecified.

Once the information from the memory devices 124 is stored in the cache404, the Hamming control logic 410 may be configured to control theprocessor 412 to compare image codes of the dataset to the image codethat was provided as part of the Hamming process request. To compare theimage codes of the dataset to the image code that was provided as partof the Hamming processing request, the Hamming control logic 410 isfurther configured to provide the processor 412 with controlinstructions to calculate a respective Hamming distance for each imagecode of the dataset and the image code that was provided as part of theHamming process request. For example, the processor 412 may utilize thestored image code at the cache 404 and the respective image codesassociated with the information retrieved from the memory devices 124,those respective images codes also being stored at the cache 404, tocalculate respective Hamming distances. In an implementation where theimage codes are binary embeddings or representations, a Hamming distancemay be calculated for each image code of the dataset and the image codeof the obtained image as provided in Equation (1), described above.Thereby, in calculating a plurality of Hamming distances, the storedimage code of the cache 404, provided as part of the Hamming processrequest, is compared to each image code representative of acorresponding image of an image dataset.

Similar to the operation of the Hamming control logic 112, the Hammingcontrol logic 410 also may be configured to apply a results algorithm,as executed by the processor 412, to identify a set of resultsindicative of certain images in the dataset that match the obtainedimage, e.g., a k-nearest neighbor algorithm, as described herein. Asadditional or alternative example implementations of such resultsalgorithms, a results algorithm may be executed by the processor 116 asa null-test, such that only a null result for a Hamming distancecalculation is included in a set of results, which set may be unitary. Aresults algorithm may additionally or alternatively utilize a set ofcriteria for a match, such as a specified tolerance of matches, a matchwith minimum error (e.g., as compared to other matches), or any errorcriteria. For example, a threshold results algorithm may use an errorupper-bound to identify matches, such that matches are defined as thosewith errors that are under the error-upper bound. Also similar to theoperation of Hamming control logic 112, the Hamming control logic 410 isconfigured to control the processor 412 to provide the set of results tohost computing device 102 via the host bus 104. For example, the set ofresults may be provided to the host computing device 102, in accordancewith control instructions of the Hamming control logic 112, as thecorresponding images of the dataset included in the set of results,again referred to as image processing results.

While examples of images codes being calculated in accordance with aHamming distance of hashed binary embedding have been described toidentity a matched image code of an obtained image, it can beappreciated that alternative hashing techniques may be utilized tocalculate image codes, such as perceptual hashing or feature hashing tocalculate image codes. Such hashing may utilize k-nn as a resultsalgorithm or alternative algorithms to compare results of calculatedimage codes. As an example of an alternative hashing technique, a Bloomfilter may be utilized to hash an obtained image and calculate imagecodes for a dataset. In the example, different than applying a modulo-2calculation as described with respect to Hamming calculations herein,images codes may be summed together, e.g., via an AND-operation toacquire sets of hashed image codes in varying distributions. Using thesummed sets of hashed image codes a control logic, like the Hammingcontrol logic 410 described herein, may identify which image codes sharea same set (e.g., a set of results) thereby indicating a match of theimage code representative of the obtained image.

In utilizing the cache 404 and memory buses 416, the memory controller402 utilizes multiple buses to access information associated with imagesof a dataset, whether image codes or images themselves, faster than aconventional system which may obtain information about the dataset overa single host bus 104 for processing at the host computing device 102.Accordingly, the system 100, advantageously, increases the rate andamount of processing of such datasets in a neural network hosted on hostcomputing device 102, as comparisons of image codes are performed“closer” to the memory devices 124, e.g., at the memory controller 402coupled to the memory devices 124 via the memory buses 416.

In various implementations, the memory controllers memory controller 402may be an NVMe memory controllers, which is coupled to the hostcomputing device 102 via the host bus 104, e.g., a PCIe bus operating inaccordance with an NVMe protocol. In such implementations, the memorydevices 124 may be NAND memory devices, which are coupled to the NVMememory controller 402 via a respective PCIe bus operating in accordancewith an NVMe protocol. Accordingly, the memory buses 416 may be referredto as NVMe memory buses. Accordingly, in comparison to a conventionalmemory system which may access memory via a single host bus to hostcomputing device 102, the system 400, advantageously, increases the rateand amount of processing by the number of NVMe memory buses 416connected to respective memory devices 124. Accordingly, the system 400may be referred to as “accelerating” Hamming distance calculations withan increase availability of data transfer over the memory buses 416.

FIG. 5 is a schematic illustration of a method 500 in accordance withexamples described herein. Example method 500 may be performed using,for example, a host computing device 102 and/or a memory controller 402may execute executable instructions to interact with the memory devices124 via memory buses 416. For example, some instructions may be executedby a host processor at host computing device 102 (e.g., blocks 502-506),while other instructions may be executed by Hamming control logic 410 atthe processor 412 (e.g., blocks 508-516). The operations described inblocks 502-516 may be stored as computer-executable instructions in oneor more computer-readable medium accessible by the host processor and/orby processor 412. For example, the executable instructions may be storedon one of the memory devices 124 and retrieved by the memory controller402. In the example, the host computing device 102 and/or itself, thememory controller 402, may execute the executable instructions forperforming the method 300. Additionally or alternatively, the executableinstructions may be stored on a memory coupled to the host computingdevice 102 and retrieved by the processor 412 to execute the executableinstructions for performing the method 500. The blocks included in thedescribed example method 500 are for illustration purposes. In someembodiments, these blocks may be performed in a different order. In someother embodiments, various blocks may be eliminated. For example, insome implementations, block 514 may be an optional block in executingmethod 500. In still other embodiments, various blocks may be dividedinto additional blocks, supplemented with other blocks, or combinedtogether into fewer blocks. Other variations of these specific blocksare contemplated, including changes in the order of the blocks, changesin the content of the blocks being split or combined into other blocks,etc.

Example method 500 may begin with block 502 that starts execution of themethod and includes an instruction to obtain an image from an IoTcomputing device. Block 502 may be executed in the same way as describedwith respect to block 302 of method 300. As described, in an exampleimplementation, the host computing device 102 may be configured toexecute, on a host processor of host computing device 102, a userapplication which is configured to obtain images from IoT device 114 orIoT device 118. Accordingly, the host computing device 102 may obtainimages as part of executing a user application that requests or utilizesimages.

Block 502 may be followed by block 504, such that the method furtherincludes an operation to generate an image code based on the using ahash. Block 504 may be executed in the same way as described withrespect to block 304 of method 300. As described, in an exampleimplementation, the host computing device 102 generates an image codefor the obtained image using a hash.

Block 504 may be followed by block 506, such that the method furtherincludes an operation to generate a Hamming process request based on aneural network request to obtain image processing results using aplurality of Hamming distances. Block 506 may be executed in the sameway as described with respect to block 306 of method 300. As described,in an example implementation, a neural network (or one or more neuralnetworks) on the host computing device 102 requests image processingresults regarding the obtained image and a dataset (e.g., an imagedataset). Accordingly, the Hamming processing request may be provided bythe host computing device 102 to the memory controller 402, which may beconfigured to execute that Hamming processing request, e.g., to interactwith memory devices 124 where the dataset is stored. In the exampleimplementation, the user application on the host computing device 102 isconfigured to generate the Hamming processing request and provide it tothe memory controller 402 for calculation of the plurality of Hammingdistances with respect to the image code.

Block 508 may be followed by block 506, such that the method furtherincludes an operation to obtain, via a host bus at a cache of a memorycontroller, an image code of a Hamming processing request to calculate aHamming distance. In the example implementation, a Hamming control logic410 at the processor 412, obtains, over the host bus 104 of the memorycontroller 402, an image code of the Hamming processing request tocalculate one or more Hamming distances. The image code may be providedto a cache 404, by the processor 412 or the host interface 408 via aninternal memory controller bus of the memory controller 402, such thatthe cache 404 obtains the image code for storage. In obtaining theHamming processing request, the cache 404 may store an image codeassociated with Hamming processing request at the cache 404.Accordingly, in various implementations, at block 508, the cache 404obtains the Hamming process request, to store an image code associatedwith the Hamming processing request.

Block 510 may be followed by block 508, such that the method furtherincludes an operation, responsive to the Hamming processing request, toprovide, at least one memory access request to a plurality of memorydevices to access information associated with the plurality of images.In the example implementation, block 510 may be executed analogously asblock 204 of method 200. In the example, the memory controller 402identifies a memory device 124 to provide the information in the Hammingprocessing request, and the processor 412 uses that identificationinformation to generate one or more memory access requests. Accordingly,the Hamming control logic 410, responsive to the Hamming processingrequest and as executed by the processor 412, generates one or morememory access requests (e.g., a read command) for the memory devices124, coupled to the memory controller 402, to access informationassociated with images in the dataset.

Block 510 may be followed by block 512, such that the method furtherincludes an operation to obtain, at the cache, a plurality of imagesfrom the plurality of memory devices. In the example implementation, thecache 404 obtains the plurality of images for processing of theplurality of images, e.g., to calculate Hamming distances, therebycomparing the stored image code at the cache 404 with each image of theplurality of images. In the example implementation of obtaining theplurality of images, the memory devices 124 may store only the images ofdataset, and not corresponding image codes. Accordingly, the pluralityof images are obtained at the cache 404, which is instructed by theHamming control logic 410, to hash the plurality of images with the samehash that was applied to the obtained image of the IoT device 114 or IoTdevice 118 to generate the image code associated with that image. Thus,the Hamming control logic 410 obtains the plurality of images from thememory devices 124 and may also hash the plurality of images to generaterespective image codes for each image of the plurality of images.

Block 514 may be followed by block 512 such that the method furtherincludes an operation to perform error correction on the obtainedplurality of images. In the example, the cache 404 provides the obtainedplurality of images (e.g., obtained from the memory devices 124) to theerror correction unit 414. The error correction unit 414 error correctsthat obtained information, and, subsequently, provides the plurality ofimages back to the same storage locations in the cache 404 aserror-corrected. As described above, block 514 may be an optional stepin some implementations of method 500.

Block 516 may be followed by block 512, such that the method furtherincludes an operation to compare, at the memory controller, at least oneimage of the plurality of images to the image code to calculaterespective Hamming distances of a plurality of Hamming distances. In theexample implementation, block 516 may be executed analogously as block206 of method 200. For example, the Hamming control logic 410 mayexecute executable instructions at the processor 412 to calculaterespective Hamming distances for each image code of the dataset obtainedat the cache 404 and the image code of the obtained image, also storedat cache 404, in accordance with Equation (1). The method 500 may endafter completion of the block 516.

FIG. 6 is a schematic illustration of a memory system 600 arranged inaccordance with examples described herein. System 600 includes a hostcomputing device 602 coupled to IoT device 604 and IoT device 608.System 600 also includes Hamming memory device 610 coupled to the hostcomputing device 102 via host bus 606. The Hamming memory device 610includes processor 614, which includes Hamming logic 612, that couplesto the host computing device 602 via the host bus 606. Processor 614 isalso coupled to input/output (I/O) control unit 618 via I/O bus 616 andcoupled to control logic 622 via control bus 620. Control logic 622interacts with other elements of the Hamming memory device 610,including memory array 624 through the data register 626 and cacheregister 628. The I/O control unit 618 also interacts with memory array624, e.g., as certain control pins are enabled at the control logic 622.For example, certain control pins depicted in FIG. 6 (e.g., Eni, CE #,CLE, ALE, WE #, RE #, WP #) may receive control signals that enableoperations of the I/O control unit 618 corresponding to that control pinfunctionality. In various implementations, the Hamming memory device 610may be a NAND memory device, and the memory array 624 may be a NANDFlash memory array. In addition the numbered elements of Hamming memorydevice 610, as will be appreciated by one of skill in the art, otherfeatures of a memory device (e.g., a NAND memory device) may be includedin Hamming memory device 610, such as the various voltages available toelements of the Hamming memory device 610 (e.g., Vpp, Vrefq, Vcc, Vss,Vccq, and/or Vssq). For example, as depicted, an address register mayinteract with I/O control unit 618 to store and/or provide memoryaddresses to access at memory array 624 using a row decoder and a columndecoder coupled to the memory array 624. Also as depicted, a statusregister may interact with I/O control unit 618 and control logic 622 tostore and/or provide a status of certain memory elements in Hammingmemory device 610. And, a command register may interact with i/O controlunit 618 and control logic 622 to store and/or provide a command fromI/O control unit 618 to control logic 622.

Additionally or alternatively, it can be appreciated that thesimilarly-named elements of system 100 and system 600 may be configuredin an analogous way, such as: host computing device 102 to hostcomputing device 602, host bus 104 to host bus 606, IoT device 114 toIoT device 604, IoT device 118 to IoT device 608, and Hamming controllogic 112 to Hamming logic 612. For example, as analogously describedwith respect to host bus 104, the host bus 606 may be a PCIe bus thatcan communicate Hamming processing commands between the host computingdevice 602 and, instead of the Hamming processing unit 108 of FIG. 1 ,the Hamming memory device 610 of FIG. 6 . Accordingly, similar asdescribed with respect to FIG. 1 , the host computing device 602 mayhost a neural network that utilizes image codes, like binary embeddings,to process neural network requests. Further, the host computing device602 may utilize a hash to generate respective image codes for theobtained images. Advantageously, in processing Hamming processingcommands on Hamming memory device 610, a rate and amount of processingof datasets (e.g., an image code dataset) in a neural network of system600, e.g., as compared to a conventional neural network processingsystem, which may first retrieve images or content from the memorydevices to process images or content at a local cache or storage deviceof the host computing device 602, introducing delays into processingspeed and processing rates.

In an example of an obtained image from the IoT device 604, the neuralnetwork on the host computing device 602 generates a Hamming processingcommand to the Hamming memory device 610, to obtain image processingresults about the obtained image using Hamming distance calculations.The generated Hamming processing command includes the hashed image codeof the obtained image. As described with respect to the host computingdevice 102 of FIG. 1 , the host computing device 602 may also utilize ahash to generate an image codes for the obtained image (e.g., a binaryembedding). Continuing in the example, the host computing device 602 mayinclude a host processor configured to execute a user applicationutilizing Hamming distance calculations to obtain image processingresults about the image code. When executed, the user applicationgenerates a Hamming processing command to perform Hamming distancecalculations on the hashed image code, to obtain the image processingresults about the obtained image. The host computing device 602 providesthe Hamming processing command to the processor 614 via the host bus606. Additionally or alternatively, in various implementations, the hostcomputing device 602 may include a memory controller 402 that providesHamming processing requests as Hamming processing commands to theHamming memory device 610 via a memory bus (e.g., a memory bus 416).

Upon obtaining the Hamming processing command at the processor 614, theHamming logic 612 may identify the Hamming processing command to providethe image code associated with the Hamming processing command to the I/Ocontrol unit 618 and to provide one or more control signals indicativeof the Hamming processing command to the control logic 622. One or morecontrol signals provided to the Hamming logic 612 can include controlsignals being provided to control logic pins of the control logic 622via the control bus 620, such as control logic pins: WE #, CLE, and/orALE. Accordingly, the control logic 622 may obtain one or more controlsignals from the Hamming logic 612 based on the Hamming processingcommand. In an example, obtaining a control signal, at the command latchenable (CLE) pin of the control logic 622, may be indicative to theHamming memory device 610 that a Hamming processing command has beenobtained. Accordingly, the control logic 622 may activate a gate of atransistor that controls a R/B # pin output that indicates a Ready/Busystatus of the memory array 624. For example, in obtaining the controlsignal at the CLE pin, the control logic 622 may provide a gate signalto a transistor such that the drain of the transistor (e.g., if a n-typetransistor) sets to high, indicative of a Busy status at the memoryarray 624. Accordingly, the control logic 622, responsive to obtainedone or more control signals indicative of the Hamming process command,may provide internal control signals to control various memory accesscircuits to perform a memory access operation (e.g., read, write,program). For example, the internal control signals may comprise one ormore memory access requests to perform memory access operations. Thememory access requests may include memory addresses of cells that are tobe accessed in performing the memory access operations.

The various memory access circuits are used during such memory accessoperations, and may generally include circuits such as row and columndecoders, charge pump circuits, signal line drivers, I/O control unit618, data register 626, and cache register 628. The memory cells in thememory array 624 may be accessed through the use of various signallines, for example, global word lines (GWLs), local word lines (LWLs),and bitlines (BLs). The memory cells may be non-volatile memory cells,such as NAND or NOR flash cells, phase change memory cells, or maygenerally be any type of memory cells. The memory cells may be singlelevel cells configured to store data for one bit of data. The memorycells may also be multi-level cells configured to store data for morethan one bit of data.

Additionally upon obtaining the Hamming processing command at theprocessor 614 and, in some implementations, contemporaneously, theHamming logic 612 may also identify the image code within the Hammingprocessing command to provide the image code to the I/O control unit618. For example, the image code may be provided to the DQ pins of theI/O control unit 618 via the i/O bus 616. In the example, the I/Ocontrol unit 618 may obtain the image code from the DQ pins when one ormore control signals at the control logic 622 are asserted. For example,a combination of control signals may be provided to the control logic622 such that the I/O control unit 618 obtains the image code to providethe image code to the cache register 628. For example, the control logic622 may obtain an additional control signal indicative that the imagecode is to be written to the data register of the memory device, andthus the I/O control unit 618 provides the image code to the cacheregister 628. In the example, the additional control signal may beobtained at the write enable (WE #) pin of the control logic 622,subsequent to when the one or more controls signals at the control logic622 are asserted to obtain the image code from the DQ pins. Inactivating the WE #pin, certain voltages (e.g., Vrefq) may be providedto the cache register 628 to enable writing of image code to the cacheregister 628 by the I/O control unit 618.

Generally, commands, address information, and write data may be providedto the memory array 624 as sets of sequential I/O transmitted throughthe various buses coupling the I/O control unit 618 and the memory array624. A DQS signal (e.g., at a DQS pin) may be used to provide timinginformation for the transfer of data to the memory array 624 or from thememory array 624. An address register coupled to the I/O control unit618 may be provided address information by the I/O control circuit I/Ocontrol unit 618 to be temporarily stored. The I/O control unit 618 mayalso be coupled to a status register storing status bits. Status bitsstored by the status register may be provided by the I/O control circuitI/O control unit 618 responsive to a read status command provided to thememory array 624, for example. The status bits may have respectivevalues to indicate a status condition of various aspects of the memoryarray 624 and its operation.

As described, the control logic 622, responsive to obtaining one or morecontrol signals indicative of the Hamming process command, provides oneor more memory access requests, including memory addresses of storedimages codes (e.g., an image code dataset) at the memory array 624, tovarious memory access circuits to perform memory access operations. Inthe example, the Hamming logic 612 generates a plurality of memoryaddresses to read based on the Hamming processing command. The pluralityof memory address are provided to the control logic 622 as data to read,e.g., via a command register as parsed by I/O control unit 618 via I/Obus 616. The control logic 622 generates one or more memory accessrequests based on the plurality of memory address obtained from thecommand register.

The Hamming logic 612 may also provide the one or more control signalsto the control logic 622 to calculate respective Hamming distances amongthe image code of the Hamming processing command and each stored imagecode of a plurality of stored image codes at the memory array 624. Incalculating a plurality of Hamming distances, the image code provided aspart of the Hamming process command is compared to each image coderepresentative of a corresponding image of an image dataset, forexample, or an image code dataset. In an implementation where the imagecodes are binary embeddings or representations, a Hamming distance maybe calculated for each stored image code and the image code of theHamming processing command as provided in Equation (1), above. Forexample, each memory access request comprising a memory address of astored image code is provided to row and column decoders of the Hammingmemory device 610 for reading the memory array 624. In the example, eachmemory address is read to the data register 626 of the Hamming memorydevice 610 to obtain the plurality of stored image codes on the dataregister 626.

To calculate each respective Hamming distance, the control logic 622controls the data register 626 to calculate, at the data register 626,each respective Hamming distance using the image code associated withthe Hamming processing command stored at the cache register 628 and theplurality of stored images codes at the data register 626. In theexample, at the data register 626, as indicated by Equation (1), a “mod2” operation, being a modulo-2 calculation, is performed after theadding of the bits of the image code and each respective stored imagecode. The results from each modulo-2 operation are summed to provide theHamming distance for a particular stored image code representing animage of an image dataset and the image code that was provided as partof the Hamming processing command. The calculated Hamming distances arestored in the cache register 628. The Hamming logic 612 providesadditional control signals to the control logic 622 such that thecalculated Hamming distances are provided to the processor 614 via theI/O bus 616 for applying a results algorithm.

To determine a match of the obtained image, a set of results may beobtained by the processor 614 by executing a results algorithm toinclude matches in the set of results, as controlled by the Hamminglogic 612. For example, the Hamming logic 612 may be configured to applya results algorithm, as executed by the processor 614, as a thresholdcomparison, such that any Hamming distance calculation passing athreshold is included in a set of results. As another example, a resultsalgorithm may be executed by the processor 614 as a null-test, such thatonly a null result for a Hamming distance calculation is included in aset of results, which set may be unitary. As yet another example, aresults algorithm may be executed by the processor 614 as a k-nearestneighbor algorithm, such that a number of neighbors in a bitwisedimensional space are selected as nearest to the image code of theobtained image based on the calculated Hamming distance calculation ofthat respective image code representative of an image of the dataset.Accordingly, any number or results algorithms may be applied to theHamming distance calculations to identify a set of results indicative ofcertain images in the dataset that match the obtained image.

While examples of images codes being calculated in accordance with aHamming distance of hashed binary embedding have been described toidentity a matched image code of an obtained image, it can beappreciated that alternative hashing techniques may be utilized tocalculate image codes, such as perceptual hashing or feature hashing tocalculate image codes. Such hashing may utilize k-nn as a resultsalgorithm or alternative algorithms to compare results of calculatedimage codes. As an example of an alternative hashing technique, a Bloomfilter may be utilized to hash an obtained image and calculate imagecodes for a dataset. In the example, different than applying a modulo-2calculation as described with respect to Hamming calculations herein,images codes may be summed together, e.g., via an AND-operation toacquire sets of hashed image codes in varying distributions. Using thesummed sets of hashed image codes a control logic, like the Hammingcontrol logic 612 described herein, may identify which image codes sharea same set (e.g., a set of results) thereby indicating a match of theimage code representative of the obtained image.

Once identified as the set of results, the Hamming logic 612 isconfigured to control the processor 614 to provide the set of results tohost computing device 602 via the host bus 606. For example, the set ofresults may be provided to the host computing device 602, in accordancewith control instructions of the Hamming logic 612, as the correspondingstored image codes included in the set of results, which may be referredto as image processing results for the Hamming memory device 610.Accordingly, the host computing device 602 may utilize the provided setof results from the Hamming memory device 610 in a neural network hostedby the host computing device 602.

FIG. 7 is a schematic illustration of a method 700 in accordance withexamples described herein. Example method 700 may be performed using,for example, a Hamming memory device 610 executes executableinstructions (e.g., by Hamming logic 612 at the processor 614) tointeract with the memory array 624. For example, the operationsdescribed in blocks 602-606 may be stored as computer-executableinstructions in a computer-readable medium accessible by processor 614.The operations described in blocks 702-706 may be stored ascomputer-executable instructions in one or more computer-readable mediumaccessible by the processor 614. For example, the executableinstructions may be stored on a memory coupled to the host 602 andretrieved by the processor 614 execute the executable instructions forperforming the method 700.

Example method 700 may begin with block 702 that start execution of themethod and includes an operation to obtain, at an I/O control unit of amemory device, an image code associated with a Hamming processingcommand. In an example implementation of the Hamming memory device 610,a Hamming processing command may be provided by a host computing device602 to a processor 614 via a host bus 606 For example, the host bus 606may be a PCIe bus that couples the Hamming memory device 610 to the hostcomputing device 602, such that the host computing device 602 mayprovide information to the Hamming memory device 610 from a userapplication, executing on a host processor, which utilizes Hammingdistance calculations and generates the Hamming processing command. Forexample, the Hamming processing command, as generated by the userapplication, may specify that Hamming distance calculations regarding animage code of an image and an image code dataset, including a pluralityof image codes, stored in the memory array 624 are to be performed; and,accordingly, requests, by virtue of the Hamming process command, thatthe Hamming logic 612 implement such calculations at the Hamming memorydevice 610. In the example, the Hamming process command may include theimage code associated with the image. The image may be an image obtainedfrom an image capture device, e.g., IoT device 604 or IoT device 608.Upon obtaining the Hamming processing command at the processor 614, theHamming logic 612 may identify the Hamming processing command to providethe image code associated with the Hamming processing command to the I/Ocontrol unit 618. Accordingly, in various implementations, at block 202,the I/O control unit 618 obtains the image code associated with theHamming process command.

Block 702 may be followed by block 704, such that the method furtherincludes an operation, responsive to the Hamming processing command, toprovide at least one memory access request for a plurality of memoryaddresses to obtain the plurality of stored image codes. In the exampleimplementation of the Hamming memory device 610, the control logic 622,responsive to obtaining one or more control signals indicative of theHamming process command, provides one or more memory access requests,including memory addresses of stored images codes (e.g., an image codedataset) at the memory array 624, to various memory access circuits toperform memory access operations. In the example, the Hamming logic 612generates a plurality of memory addresses to read based on the Hammingprocessing command. The plurality of memory address are provided to thecontrol logic 622 as data to read to the data register 626. In theexample, each memory address is read to the data register 626 of theHamming memory device 610 to obtain the plurality of stored image codeson the data register 626.

Block 704 may be followed by block 706, such that the method furtherincludes an operation to compare each stored image code of the pluralityof stored image codes to the image code associated with the Hammingprocessing command to calculate respective Hamming distances of aplurality of Hamming distances. In the example implementation of theHamming memory device 610, the control logic 622 controls the dataregister 626 to calculate, at the data register 626, each respectiveHamming distance using the image code associated with the Hammingprocessing command stored at the cache register 628 and the plurality ofstored images codes at the data register 626. For example, the Hammingcontrol logic 622 may execute executable instructions at the processor614 to calculate respective Hamming distances for each image code of thedataset and the image code of the obtained image in accordance withEquation (1). Accordingly, each Hamming distance calculation isrepresentative of the image code being compared to one of the pluralityof stored image codes. The method 200 may end after completion of theblock 206.

FIG. 8 illustrates an example of a system 800 in accordance with aspectsof the present disclosure. The system 800 includes a person 802 and avehicle 804 with a person 806. System 800 also includes an IoT device808 adhered to a house 810 and may be communicatively coupled to thehouse 810, e.g., via a wired connection (not depicted). The house 810,which may include a network endpoint, is coupled to a network switch 814that couples the house 810 to data center 820. For example, the house810 may be coupled to the network switch 814 via a wired (e.g., fiberoptic, Ethernet) and/or wireless connection (e.g., Wi-Fi, Bluetooth).The IoT device 808 may also be communicatively coupled via a wirelessconnection to a wireless endpoint 812. For example, the wirelessconnection for the IoT device 808 may be a narrowband wirelesscommunication connection in accordance with a Narrow Band IoT (NB-IoT)5G standard. The wireless endpoint 812 is coupled via a wired connection(e.g., a fiber optic cable) to the data center 820. The data center 820includes a host computing device 816 coupled to a memory system 822 thatinteracts with the memory devices 824.

The IoT device 808 may be an image capture device that obtains an imageof the person 802, the vehicle 804, and/or the person 806 in the vehicle804, e.g., as the person 802 or vehicle 804 approaches the house 810. Inthe example, the IoT device 808 may obtain an image of the person 802,e.g., to compare an image of that person 802 to an image of anindividual in a dataset of convicted criminals (e.g., a dataset ofimages of convicted violent or sexual offenders). In the example, animage of the vehicle 804 may be obtained by the IoT device 808 tocompare the image of that vehicle 804 (or a portion thereof, e.g., animage of the license plate) to a dataset of license plates, e.g.,license plates associated with active Amber alerts (e.g., a governmentalert regarding an abducted or kidnapped child). Accordingly, the IoTdevice 808 may obtain images of individuals or vehicles, which aresurrounding or approaching house 810. The house 810, having a networkendpoint, may communicate the obtained images to a data center 820 viathe network switch 814 or via a wireless connection to wireless endpoint812.

Once the obtained image is provided to the data center 820, the hostcomputing device 816 may generate a Hamming process request, e.g., inprocessing that obtained image on a neural network hosted by hostcomputing device 816 and interacting with memory system 822. The memorysystem 822 may calculate Hamming distances of an image code of thatobtained image with corresponding image codes of images in a relevantdataset stored on memory devices 824. Additionally or alternatively, theIoT device 808 may process that obtained image on a memory device(s)itself of the IoT device 808. In the example, the IoT device 808includes a memory device implementing the Hamming memory device 610,e.g., to calculate Hamming distances of an image code of that obtainedimage with corresponding image codes of images in a relevant datasetstored on a memory device of the IoT device 808 itself. Advantageously,in processing Hamming processing commands on a memory device of the IoTdevice 808 itself, rate and amount of processing of datasets in a neuralnetwork at the IoT device 808 itself is increased, e.g., as compared toa conventional neural network processing system, which may firstretrieve images or content from the memory devices to process images orcontent at a local cache or storage device, introducing delays intoprocessing speed and processing rates.

The system 800 facilitates the processing of datasets that may beexecuted by neural networks hosted on host computing device 816 at thedata center 820. In the example, the memory system 822 may implement aHamming processing unit 108, e.g., using the memory devices 824; or, thememory system 822 may implement a memory controller 402. In either case,such implementation increases processing capacity of the calculationsperformed for the neural networks, e.g., as comparisons of image codescan be performed “closer” to the memory devices 824 by implementing thememory system 822 as a processing unit having memory devices 824 (e.g.,as Hamming processing unit 108) or as a memory controller (e.g., memorycontroller 402) coupled to the memory devices 824. In the example, thememory system 822 is closer to the memory devices 824 as compared to,for example, a conventional system which may retrieve and store datasetsfrom the memory devices 824 on the host computing device 816 forprocessing of datasets or a conventional system which may retrieve andstore images to be processed at the house 810 network endpoint from thedata center 820. In the implementation of memory system 822 being aHamming processing unit 108, the comparisons of image codes areperformed at the Hamming processing unit 108 having the memory devices124 via controller buses 120 and respective memory buses 122. Forexample, the memory system 822 may implement the method 200 or method300, as a Hamming processing unit 108 having the memory devices 824, toobtain a set of results regarding an image obtained by the IoT device808. As another example, the memory system 822 may implement the method500 at the Hamming control logic 420 of the Hamming processing unit 108having the memory devices 824, to obtain a set of results regarding animage obtained by the IoT device 808.

Advantageously, in distributing the Hamming processing requests to thememory devices 824 when implementing the memory system 822 as Hammingprocessing unit 108 or memory controller 402, the memory system 822facilitates an increased rate of processing of datasets by usingavailable memory buses coupled to the memory system 822, such as memorybuses operating in accordance with an NVMe protocol.

Certain details are set forth above to provide a sufficientunderstanding of described examples. However, it will be clear to oneskilled in the art that examples may be practiced without various ofthese particular details. The description herein, in connection with theappended drawings, describes example configurations and does notrepresent all the examples that may be implemented or that are withinthe scope of the claims. The terms “exemplary” and “example” as may beused herein means “serving as an example, instance, or illustration,”and not “preferred” or “advantageous over other examples.” The detaileddescription includes specific details for the purpose of providing anunderstanding of the described techniques. These techniques, however,may be practiced without these specific details. In some instances,well-known structures and devices are shown in block diagram form inorder to avoid obscuring the concepts of the described examples.

Information and signals described herein may be represented using any ofa variety of different technologies and techniques. For example, data,instructions, commands, information, signals, bits, symbols, and chipsthat may be referenced throughout the above description may berepresented by voltages, currents, electromagnetic waves, magneticfields or particles, optical fields or particles, or any combinationthereof.

Techniques described herein may be used for various wirelesscommunications systems, which may include multiple access cellularcommunication systems, and which may employ code division multipleaccess (CDMA), time division multiple access (TDMA), frequency divisionmultiple access (FDMA), orthogonal frequency division multiple access(OFDMA), or single carrier frequency division multiple access (SC-FDMA),or any a combination of such techniques. Some of these techniques havebeen adopted in or relate to standardized wireless communicationprotocols by organizations such as Third Generation Partnership Project(3GPP), Third Generation Partnership Project 2 (3GPP2) and IEEE. Thesewireless standards include Ultra Mobile Broadband (UMB), UniversalMobile Telecommunications System (UMTS), Long Term Evolution (LTE),LTE-Advanced (LTE-A), LTE-A Pro, New Radio (NR), IEEE 802.11 (WiFi), andIEEE 802.16 (WiMAX), among others.

The terms “5G” or “5G communications system” may refer to systems thatoperate according to standardized protocols developed or discussedafter, for example, LTE Releases 13 or 14 or WiMAX 802.16e-2005 by theirrespective sponsoring organizations. The features described herein maybe employed in systems configured according to other generations ofwireless communication systems, including those configured according tothe standards described above.

The various illustrative blocks and modules described in connection withthe disclosure herein may be implemented or performed with ageneral-purpose processor, a digital signal processor (DSP), anapplication-specific integrated circuit (ASIC), a field-programmablegate array (FPGA), or other programmable logic device, discrete gate ortransistor logic, discrete hardware components, or any combinationthereof designed to perform the functions described herein. Ageneral-purpose processor may be a microprocessor, but in thealternative, the processor may be any conventional processor,controller, microcontroller, or state machine. A processor may also beimplemented as a combination of computing devices (e.g., a combinationof a DSP and a microprocessor, multiple microprocessors, one or moremicroprocessors in conjunction with a DSP core, or any other suchconfiguration).

The functions described herein may be implemented in hardware, softwareexecuted by a processor, firmware, or any combination thereof. Ifimplemented in software executed by a processor, the functions may bestored on or transmitted over as one or more instructions or code on acomputer-readable medium. Computer-readable media includes bothnon-transitory computer storage media and communication media includingany medium that facilitates transfer of a computer program from oneplace to another. A non-transitory storage medium may be any availablemedium that can be accessed by a general purpose or special purposecomputer. By way of example, and not limitation, non-transitorycomputer-readable media can comprise RAM, ROM, electrically erasableprogrammable read only memory (EEPROM), or optical disk storage,magnetic disk storage or other magnetic storage devices, or any othernon-transitory medium that can be used to carry or store desired programcode means in the form of instructions or data structures and that canbe accessed by a general-purpose or special-purpose computer, or ageneral-purpose or special-purpose processor.

Also, any connection is properly termed a computer-readable medium. Forexample, if the software is transmitted from a website, server, or otherremote source using a coaxial cable, fiber optic cable, twisted pair,digital subscriber line (DSL), or wireless technologies such asinfrared, radio, and microwave, then the coaxial cable, fiber opticcable, twisted pair, DSL, or wireless technologies such as infrared,radio, and microwave are included in the definition of medium.Combinations of the above are also included within the scope ofcomputer-readable media.

Other examples and implementations are within the scope of thedisclosure and appended claims. For example, due to the nature ofsoftware, functions described above can be implemented using softwareexecuted by a processor, hardware, firmware, hardwiring, or combinationsof any of these. Features implementing functions may also be physicallylocated at various positions, including being distributed such thatportions of functions are implemented at different physical locations.

Also, as used herein, including in the claims, “or” as used in a list ofitems (for example, a list of items prefaced by a phrase such as “atleast one of” or “one or more of”) indicates an inclusive list suchthat, for example, a list of at least one of A, B, or C means A or B orC or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein,the phrase “based on” shall not be construed as a reference to a closedset of conditions. For example, an exemplary step that is described as“based on condition A” may be based on both a condition A and acondition B without departing from the scope of the present disclosure.In other words, as used herein, the phrase “based on” shall be construedin the same manner as the phrase “based at least in part on.”

From the foregoing it will be appreciated that, although specificexamples have been described herein for purposes of illustration,various modifications may be made while remaining with the scope of theclaimed technology. The description herein is provided to enable aperson skilled in the art to make or use the disclosure. Variousmodifications to the disclosure will be readily apparent to thoseskilled in the art, and the generic principles defined herein may beapplied to other variations without departing from the scope of thedisclosure. Thus, the disclosure is not limited to the examples anddesigns described herein, but is to be accorded the broadest scopeconsistent with the principles and novel features disclosed herein.

What is claimed is:
 1. A method comprising: responsive to request tocalculate a Hamming distance among a plurality of images and a targetimage associated with an image code received from a host computingdevice, providing at least one memory access request to a plurality ofmemory devices to access information associated with the plurality ofimages stored at the plurality of memory devices; and calculating arespective Hamming distance of a plurality of Hamming distances bycomparing an image of the plurality of images to the image code.
 2. Themethod of claim 1, further comprising receiving the request to calculatethe Hamming distance obtaining via a host bus.
 3. The method of claim 2,further comprising receiving the request to calculate the Hammingdistance obtaining at Hamming control logic.
 4. The method of claim 2,further comprising receiving the request to calculate the Hammingdistance obtaining at a processor.
 5. The method of claim 1, furthercomprising generating the image code based on the target image using ahash.
 6. The method of claim 1, further comprising receiving the imagefrom an Internet of Things (IoT) computing device.
 7. The method ofclaim 6, wherein the IoT computing device comprises at least one of acamera, a smartphone device, or an image capture device.
 8. The methodof claim 1, wherein the Hamming processing request is generated based ona neural network request to obtain image processing results using theplurality of Hamming distances.
 9. The method of claim 1, furthercomprising accessing, from the plurality of memory devices, a respectiveimage code for an image of the plurality of images as the informationassociated with the plurality of images.
 10. The method of claim 1,further comprising hashing the at least one image of the plurality ofimages to generate at least one hashed image code for that respectiveimage to calculate the respective Hamming distance of the plurality ofHamming distances.
 11. An apparatus comprising: Hamming control logiccircuitry configured to, responsive to request to calculate a Hammingdistance among a plurality of images and a target image associated withan image code received from a host computing device, provide at leastone memory access request to a plurality of memory devices to accessinformation associated with the plurality of images stored at theplurality of memory devices, wherein the Hamming control logic circuitryis further configured to calculate a respective Hamming distance of aplurality of Hamming distances by comparing an image of the plurality ofimages to the image code to.
 12. The apparatus of claim 11, wherein theHamming control logic circuitry is further configured to receive therequest to calculate the Hamming distance obtaining via a host bus. 13.The apparatus of claim 11, wherein the Hamming control logic circuitryis further configured to receive the Hamming processing request via aPCIe bus.
 14. The apparatus of claim 11, further comprising a processorincluding the hamming control logic circuitry.
 15. The apparatus ofclaim 11, wherein the image code is generated based on the target imageusing a hash.
 16. The apparatus of claim 11, wherein the image isreceived from an Internet of Things (IoT) computing device.
 17. Theapparatus of claim 11, wherein the IoT computing device comprises atleast one of a camera, a smartphone device, or an image capture device.18. The apparatus of claim 11, wherein the Hamming processing request isgenerated at the host computing device based on a neural network requestto obtain image processing results using the plurality of Hammingdistances.
 19. The apparatus of claim 11, wherein the Hamming controllogic circuitry is further configured to access, from the plurality ofmemory devices, a respective image code for an image of the plurality ofimages as the information associated with the plurality of images. 20.The apparatus of claim 11, wherein the Hamming control logic circuitryis further configured to hash the at least one image of the plurality ofimages to generate at least one hashed image code for that respectiveimage to calculate the respective Hamming distance of the plurality ofHamming distances.